1. Field of the Invention
The present invention relates to a liquid crystal driving device and a driving method thereof, and more particularly to a liquid crystal driving device driving liquid crystal so that an image is displayed uniformly throughout all of a liquid crystal screen, and a driving method thereof.
2. Description of the Prior Art
Recently, TFT-LCD (Thin Film Transistor Liquid Crystal Display) technology has been developed to secure a lower price, a lighter weight, a lower power, and higher reliability. Therefore, a line-on-glass type (hereinafter, referred to “LOG-type”) of liquid crystal display device has been developed and produced, the LOG-type liquid crystal display device having a lower substrate on which signal line patterns are formed so as to provide a pertinent drive signal and a pertinent data signal to each of a plurality of gate driver ICs (Integrated Circuits) and a plurality of source driver ICs, without a gate Printed Circuit Board (hereinafter, the Printed Circuit Board is referred to “PCB”) and a Flexible Printed Circuit board (hereinafter, referred to “FPC”).
FIG. 1 is a view illustrating a LOG-type liquid crystal display device without a gate PCB in accordance with the prior art. As shown in FIG. 1, the LOG-type liquid crystal display device includes: a liquid crystal panel 10 formed by combining an upper substrate 10a and a lower substrate 10b, with liquid crystal interposed between the substrates 10a and 10b; a source PCB 12; a plurality of source driver ICs 16, each of which is packaged in a TCP (Tape Carrier Package) 14, electrically connecting the source PCB 12 with one side portion of the lower substrate 10b; a plurality of gate driver ICs 20 packaged in TCPs by ones and electrically connected to another side portion of the lower substrate 10b; and signal line patterns 22 formed along bonding portion of the TCPs 18 and the gate driver ICs 20 so as to provide a power, a drive signal, and control signals for driving the gate driver ICs 20.
The liquid crystal panel 10 includes: a plurality of data lines DLs arranged in a column direction; a plurality of gate lines GLs arranged in a row direction; a plurality of thin-film transistors STs arranged with a matrix pattern in regions of intersection of the data lines DLs and the gate lines GLs; and liquid crystal capacities CLC formed between each of the thin-film transistors STs and a common electrode. Also, the liquid crystal panel 10 is constructed in such a manner that gate-on/off signals provided through the source driver PCB 12 so as to drive the gates of the thin-film transistors STs are applied to the gate lines GLs in sequence through the signal line patterns 22, and a data signal applied through the source driver ICs 16 is applied to the data lines DLs. The TCP may be replaced by a COF (Chip on Film).
FIG. 2 is a detailed view of the signal line patterns 22 shown in FIG. 1, in which the same reference numerals are used to designate the same or similar components. In FIG. 2, a reference numeral 24 designates a plurality of output channels for transmitting a drive signal, which is outputted from the gate driver ICs 20, to the liquid crystal panel 10.
In the conventional liquid crystal display device having such a construction, the signal line patterns 22 include a resistance component, and the values of the resistance component R1 and R2 are determined in accordance with material, thickness, and width of used metal. For example, in the case of an amorphous silicon thin-film transistor LCD (a-Si TFT LCD), a resistance value of the signal line patterns 22 ranges from a few ohms to hundreds of ohms. In particular, when the signal line patterns are formed on the liquid crystal panel 10, the resistance value is increased because are for pattern formation is small. Therefore, whenever a gate drive signal for switching on/off the gate of the FTF ST passes each of the gate driver ICs, a voltage drop—a phenomenon which its voltage level is gradually decreased—necessarily occurs.
FIG. 3 is a waveform view showing gate drive signals of gate driver ICs in accordance with the prior art. In FIG. 3, a reference character “GD1” designates a first gate drive signal of a first gate driver IC, a reference character “GD2” designates a second gate drive signal of a second gate driver IC, and a reference character “GD3” designates a third gate drive signal of a third gate driver IC.
As shown in FIG. 3, a level of a gate-off voltage VGO1 of the first gate driver IC is changed by flowing current and resistance of the signal line patterns 22, while the level of a gate-off voltage is more and more increased according to approach to the gate driver IC of the final end. To be more specific, a level of a second gate-off voltage VGO2 of the second gate driver IC rises to a higher level as compared to the level of the first gate-off voltage VG01 of the first gate driver IC, and a level of a third gate-off voltage VGO3 of the third gate driver IC rises to a higher level as compared to the level of the second gate-off voltage VGO2 of the second gate driver IC.
Meanwhile, like the case of the signal line patterns 22 for applying a gate drive signal, delay of data voltage signal is caused also in other signal line patterns (not shown), which is formed on one side portion of the lower substrate 10b of the liquid crystal panel 10 so as to apply a data signal to the data lines DLs, due to impedances of the signal lines itself and data lines DLs.
Such voltage drop and signal delay caused by the signal line patterns decrease amplitude of a gate drive signal, and causes variance in charge quantity and leakage quantity of data voltage according to an on/off characteristic curve of the TFT (Thin-Film Transistor). Such a phenomenon becomes more and more severe due to increase in length of the signal lines, which is caused according to development tendencies of liquid crystal display devices towards high resolution, large scale, and decrease of charging time (one horizontal period) due to increase of frame frequency. As a result, it cause a screen quality problem, such as a block phenomenon showing that blocks of gate driver ICs display different brightness from each other, variation of uniformity and flicker between an upper end and a lower end of a screen, and degradation of response speed.
A variety of methods may be used to solve the problem described above. One method of them is to compensate the rise of the gate-off level by extending the width of the signal line patterns 22 so that resistance value lessens. However, it is difficult to apply this method to practical use because of constraint condition on design. That is, it is because the area for forming the signal line patterns 22 in the lower substrate of the liquid crystal display device is limited, also because the width of the signal line patterns 22 formed on a bonding portion of the gate driver ICs 20 is narrow.
Another method is to sufficiently secure area for forming the signal line patterns 22 in the lower substrate by extending size of the liquid crystal panel. However, this is not matched with recent request for a low price and a light weight, and also causes another problem in that it is difficult to correspond to an international standard in size of goods.
Still another method is to coincide a resistance value of an inside signal line patterns existed in the gate driver ICs 20 with that of the signal line patterns of the panel so that non-uniformity of a screen caused at boundary faces among the gate driver ICs 20 is reduced. However, this method has an economic problem in that design of the gate driver ICs 20 must be changed every time according to several variables, such as size and resolution of a liquid crystal panel, etc.
FIG. 4 is a view showing data waveforms and charging curves of pixels of each gate line in a liquid crystal display device according to the prior art. In FIG. 4, a reference numeral 1 designates a gate voltage waveform applied to an upper end of gate lines, a reference numeral 2 designates a data voltage waveform applied to the upper end of gate lines, and a reference numeral 3 designates a charge voltage of a pixel in the upper end of gate lines. Also, a reference numeral 1′ designates a gate voltage waveform applied to a lower end of gate lines, a reference numeral 2′ designates a data voltage waveform applied to the lower end of gate lines, and a reference numeral 3′ designates a charge voltage of a pixel in the lower end of gate lines.
As shown in FIG. 4, gate-on voltage decrease of ΔVGon causes decrease of gate-on current, gate-off voltage decrease of ΔVGoff causes increase of leakage current, and charging quantity as much as ΔVC is decreased.
FIG. 5 is a view showing a characteristic curve of data currents according to gate voltages in a liquid crystal display device in accordance with the prior art. In FIG. 5, a reference character ‘a’ designates a current characteristic region when the gate-on voltage is applied, and a reference character ‘b’ designates a leakage current characteristic region when the gate-off voltage is applied.
FIG. 6 is a view showing charge voltages of data according to gate lines in a liquid crystal display device in accordance with the prior art. Herein, X-axis designates gate lines and Y-axis designates charge voltages. Also, in FIG. 6, a reference character ‘d’ designates a desired charge voltage level, a reference character ‘e’ designates real charge voltage levels, and a reference character ‘f’ designates a region in which a block phenomenon is caused.
As shown in FIG. 6, in each of the gate lines driven by a plurality of gate drivers (Driver0, Driver1, Driver2), decrease of charge voltage in accordance with signal delay of the data lines is caused.